Power management is an increasingly important aspect of processor design. For mobile and battery powered applications, for example, minimizing power consumption to maximize battery life is often a key design parameter. In addition, in high performance applications such as supercomputers and massively parallel computers, hundreds or thousands of processors may be arranged in close proximity to one another and generate a substantial amount of heat and consume a substantial amount of power, so controlling power consumption to manage power and heat output is also of considerable importance in these applications.
In some conventional processing architectures the amount of components that may be configured on a processor may exceed the amount of components that may be powered at a particular time, or the combined power consumption of the components may exceed desired thresholds. In these conventional processors, power generally needs to be distributed such the appropriate components are powered at the appropriate times. In conventional systems, power may be distributed to different dedicated areas comprising a plurality of components dedicated to a particular processing task (e.g., a dedicated graphics processing unit group of components) of the processor. However, such wide granularity power distribution generally fails to address the quickly changing power needs of individual components. The inability to address power distribution at the component level generally leads to low performance.
Some processor architectures may include IP blocks, where an IP block generally represents a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the processor. In general, IP blocks comprise reusable units of logic, cell, or chip layout design and may be considered logic cores that can be formed as ASIC chip designs or FPGA logic designs. As such, in general, an IP block may be considered a component of a processor.
To address such scenarios, a processor may be designed to support the maximum power needed if every component of the processor were consuming the maximum amount of power; however, a processor designed to support the maximum power needed generally requires more area dedicated to power support and reduces the amount of area available for processing components. In addition, such processors generally consume more power than is actually required to perform all the processing functions required of the processor.
Therefore, a continuing need exists in the art for power distribution systems and methods in processor architectures.